Now to build and test the dividers.
As per Robby's website:
The Dividers stage takes in the local oscillator's signal and divides it by 4, producing two output signals. Each output signal is at a frequency that is ¼ the stage's input signal and is a square wave with 50% duty cycle. The 50% duty cycle is with respect to the regular 5V rail.
The signals are "in quadrature", that is, they are 90° out of phase with each other. These are provided to the TX and RX mixer stages as clocking signals. They are called out on testpoints marked "QSD Clk (1 or 2)", for the I and Q signals to mix down the incoming "chunk" of RF, and "QSE Clk (1 or 2)", for the I and Q signals which mix up the PC's line out signals.On the underside two components the 74AC74 IC (U5), one decoupling capacitor
On top just two resistors added to connect to bias the offset into the divider. So the mid point signal is 50% the VCC of U5.
The Divider is tested by looking at a few things:
Check the voltage divider network across those two resistors is at 50% either side.
I get 4.99V mav and 2.49V at half way so that is right. You measure these at the hairpin bends of the two resistors R13 and R14.
Grabbing some food... back after eaten.